Manufacture of semiconductor device

  • Inventors: ITO MASAHIKO
  • Assignees: Sony Corp
  • Publication Date: June 03, 1988
  • Publication Number: JP-S63131576-A

Abstract

PURPOSE: To obtain LDD structure having precise size through a simple method by forming a gate electrode having the different length of upper and lower sides in a cross section parallel with the direction of gate length, implanting the ions of an impurity in low concentration so as to be passed through the longer side and implanting the ions of an impurity in high concentration so as not to be passed through the longer side. CONSTITUTION: A gate oxide film 2 is formed onto the surface of a p-type Si substrate 1, a polycrystalline Si layer 3 is grown, and a photo-resist layer 5 is applied and patterned. The polycrystalline Si layer 3 is etched in an isotropic manner, using the photo-resist layer 5 as a mask, and the polycrystalline Si layer 3 is formed to a tapered shape. When an SiO 2 layer 2' is grown on the surface of the polycrystalline Si layer 3 through thermal oxidation and P + ions are implanted to shape n - regions, implanted ions pass through one part of the oxide film of the side wall of a gate electrode, thus forming an n - ion implantation regions to a shape that an upper end intrudes to the gate electrode side. When As + ions are implanted to shape n + source-drain regions, the acceleration voltage of ions is controlled, and the n + regions are not brought into contact with the n - regions. COPYRIGHT: (C)1988,JPO&Japio

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    DE-4012680-A1October 25, 1990Mitsubishi Electric CorpSteuerungsschaltung fuer ein stellglied
    US-5004080-AApril 02, 1991Mitsubishi Denki Kabushiki KaishaControlling circuit for actuator
    US-5100820-AMarch 31, 1992Oki Electric Industry Co., Ltd.MOSFET fabrication process with lightly-doped drain using local oxidation step to pattern gate electrode
    US-5219782-AJune 15, 1993Texas Instruments IncorporatedSublithographic antifuse method for manufacturing
    US-6417543-B1July 09, 2002Semiconductor Energy Laboratory Co., Ltd.MIS semiconductor device with sloped gate, source, and drain regions
    US-6984551-B2January 10, 2006Semiconductor Energy Laboratory Co., Ltd.MIS semiconductor device and method of fabricating the same
    US-7351624-B2April 01, 2008Semiconductor Energy Laboratory Co., Ltd.MIS semiconductor device and method of fabricating the same